Modern computer processors typically provide support for virtual memory. In a computer processor which utilizes virtual memory, a virtual address is a memory address which does not point to a physical memory address. Instead, the virtual address first needs to be translated into a physical memory address before data on a physical device can be accessed. Virtual memory facilitates application programming because it hides fragmented physical memory addresses from computer applications. Memory management usually employs a page table which serves to translate virtual addresses into physical addresses. Because access to the page table is comparatively slow, virtual addresses which have been recently accessed are stored in a translation lookaside buffer. A translation lookaside buffer is a type of cache memory which allows for quick data retrieval. When data is to be read from or written to a virtual memory address, a computer processor may initially access its translation lookaside buffer. The translation lookaside buffer returns a physical address which corresponds to the virtual address. Data which is stored at the physical address may then be accessed.
Modern computer processors typically feature at least one cache memory other than a translation lookaside buffer. Such a cache memory does not store virtual memory addresses, but instead mirrors data which is stored in a main memory of a computer system. Because access to the main memory is comparatively slower than access to the cache memory, it is preferable if data can be retrieved from the cache memory. Computer processors typically feature a cache hierarchy with multiple cache memories. In order to allow quick access to its cache memory without the need to translate a virtual memory address into a physical memory address, the data in some cache memories may be tagged by means of virtual addresses instead of physical addresses.
During normal system operation, the data contained within the translation lookaside buffer may become outdated, for instance because of a context switch of a user application. The information for address translation which is stored in the translation lookaside buffer may therefore become invalid. This also means that address information which is currently stored in any cache memory that employs virtual addresses in order to identify data may now also be invalid. Therefore, any such entries in the cache memory may now have to be invalidated. The process of invalidation of a cache memory is called a translation lookaside buffer purge. It invalidates entries in the cache memory which contain outdated and therefore incorrect virtual addresses.
However, when a translation lookaside buffer purge is started, there may still remain data which is queued to be written into the cache memory. For instance, this may be data which is currently being requested from another data cache within the cache hierarchy. For instance, supposing that a processor has a level one cache, a level two cache and a level three cache, when data is requested from the level three cache and there is a cache hit in the level three cache, then the data which has been successfully retrieved from the level three cache may also be stored into the level one cache and into the level two cache by an update process. This ensures that the level one cache and the level two cache always contain data which has been read recently from the level three cache. However, when a translation lookaside buffer purge is active concurrently to said update process, then update operations which are performed by the update process may conflict with operations for performing the translation lookaside buffer purge. For instance, virtual addresses which have been successfully invalidated by the translation lookaside buffer purge may be overwritten by the update process afterwards. As a result, the level one cache may contain invalid virtual address information after the translation lookaside buffer purge has been completed. Additionally, cache memories usually do not allow simultaneous write access by multiple processes.
A common way to avoid the aforementioned problems is to wait for all requests to the level three cache and the corresponding update operations to complete before the translation lookaside buffer purge process is started. However, this usually causes a high delay because accessing the level three cache memory has a comparatively high access latency. Typically, the access latency of any request to the level three cache is higher than the amount of time required to perform the complete translation lookaside buffer purge. Therefore, waiting for all update operations to complete has the disadvantage that it requires a long amount of time. Alternatively, the purge operation may be started immediately, discarding all pending requests to the level three cache. However, in this case, responses from the level three cache are lost and the same requests have to be issued again at a later time. This causes a delay after the purge operation. Additionally, in a multicore processor, multiple cores which run different threads may make use of the same cache hierarchy. In many cases, only the virtual addresses which correspond to one thread running on one processor core of a computer processor have to be updated. Therefore, only these addresses are subject to a translation lookaside buffer purge. The method as previously described has the disadvantage that threads running on different cores are effectively blocked if their requests to the level three cache are discarded.